Article ID: 000075461 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is there skew across a data bus driven by a PLL in source-synchronous compensation mode?



In the Quartus® II software versions 6.1 to 7.1 SP1, when you use source-synchronous compensation, the Quartus II software automatically sets the IOE input-to-register delay for the compensated data path bit to "0".  However, the default setting for the IOE input-to-register delay for the rest of the bits in the data bus is the maximum setting. Thus, the compensated bit has a different timing delay than the rest of the bus.

To see if you are affected by this issue, check the delay setting in the Compilation report. Under Fitter, in the Resource Section, open the Delay Chain Summary. Verify that the delay for each bit in the bus is set to "0". If the delay setting is non-zero, use the Assignment Editor to set the “Input Delay from Pin to Input Register” to "0" for all the affected bus bits clocked by the PLL in source-synchronous compensation mode.

This issue is fixed beginning with the Quartus II software version 7.2. PLL source synchronous compensation applies to all inputs fed by the compensated output of the PLL and you do not have to change the input-to-register delay settings. 

Related Products

This article applies to 6 products

Cyclone® III FPGAs
Cyclone® II FPGA
Arria® GX FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Stratix® III FPGAs