Article ID: 000075446 Content Type: Product Information & Documentation Last Reviewed: 12/31/2013

How should I control the rateswitch port in PCI Express (PIPE) x4 and x8 configurations for Stratix IV GX device?

Environment

  • Stratix® IV FPGAs
  • Stratix® IV GX FPGA
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Description

When you instantiate the Stratix® IV GX transceiver in PCI Express (PIPE) x4 and x8 configurations for Gen2 data rate, the ALTGX MegaWizard® Plug-in Manager provides the rateswitch  input port that is four bits and eight bits wide, respectively.

 

Altera has identified that asserting the rateswitch[0] port performs the rateswitch function when you simulate the above configurations. The remaining bits of the rateswitch port (rateswitch[7:1] for PCI Express (PIPE) x8 configuration and rateswitch[3:1]  for PCI Express (PIPE) x4 configuration) are not functional.

 

Workaround: Altera recommends that you connect all the bits except rateswitch[0] to zero. 

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