Article ID: 000075441 Content Type: Troubleshooting Last Reviewed: 12/17/2018

When using the Low Latency Ethernet 10G MAC Intel® FPGA IP, why does the avalon_st_rx_pfc_pause_data signal de-assert for only one clock cycle after receiving an XON request in Priority-based Flow Control (PFC) implementation?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Cyclone® 10 FPGAs
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem with the Intel® Quartus® Prime software version 18.0 and earlier, the Low Latency Ethernet 10G MAC Intel® FPGA IP's avalon_st_rx_pfc_pause_data signal is de-asserted for only one clock cycle after receiving an XON request in PFC implementations. The avalon_st_rx_pfc_pause_data signal continues to be asserted until the pause quanta expire or become zero.

    Resolution

    No workaround available. 

    This problem has been fixed starting in the Intel® Quartus® Prime Pro version 18.1.

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