Article ID: 000075437 Content Type: Troubleshooting Last Reviewed: 04/24/2017

Why does my Intel Arria 10 Hard IP for PCI Express fail to send TS1 ordered sets or EIOS, and does not indicate link down, on entry to disabled state?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the Intel® Arria® 10 Hard IP for PCI Express®, you will see no TS1 ordered sets or EIOS when the LTSSM enters the disabled state. The signal dl_up will also not de-assert in the disabled state. 

    Resolution

    This problem is not scheduled to be fixed in any future Quartus® Prime software release. As a workaround, you can ignore the dl_up signal when the LTSSM is in the disabled state. 

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