Article ID: 000075433 Content Type: Troubleshooting Last Reviewed: 09/11/2012

When using the APEX™ II device, can I have an output clock in the LVDS transmitter or receiver blocks?


Description You cannot place non-differential output pins within two I/O pads of the LVDS receiver or LVDS transmitter blocks when utilizing differential signaling in them, nor can you place single-ended outputs on any pins within the LVDS blocks when differential signaling is used on any of the channels. Switching outputs on these pins could affect the True-LVDS pins and degrade performance.

The only exception to this is the PLL LOCK pin, because it rarely changes. Output pins must be at least two pads away from the LVDS receiver or transmitter blocks, unless separated by a power or ground pin.

The same two-pad rule also applies to the dedicated LVDS clock pins and the global clock pins when using differential signaling. You cannot place output pins within two pads of the LVDS clock pins (both dedicated and non-dedicated) unless separated by a power or a ground pin. You can use any unused True-LVDS pins as input pins without compromising the acceptable noise level on the VCCIO plane. Use the Show Pads view in the Quartus® II Floorplan Editor to see the pad order.

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Apex™ II