Why do I see timing violations in the Intel® Arria® 10 and Intel® Cyclone® 10 HDMI design example?

When you generate and compile HDMI design example for the Intel® Arria® 10 and Intel® Cyclone® 10 FPGAs, you might encounter timing violation due to the clock domain crossing for the following path:

From Node:
*|hdmi_0|u_bitec_hdmi_rx|SCDC_TMDS_CONFIG[1]

To Node:
*|hdmi_0|u_bitec_hdmi_rx|Alignment_Deskewing.hdmi_align_deskew|bit_slip[1].bitslipper|index[*]

To work around this problem, please add the following constraint to the SDC file:

set_multicycle_path -end -setup -from *|hdmi_0|u_bitec_hdmi_rx|SCDC_TMDS_CONFIG[1] -to *|hdmi_0|u_bitec_hdmi_rx|Alignment_Deskewing.hdmi_align_deskew|bit_slip[*].bitslipper|index[*] 2

set_multicycle_path -end -hold -from *|hdmi_0|u_bitec_hdmi_rx|SCDC_TMDS_CONFIG[1] -to *|hdmi_0|u_bitec_hdmi_rx|Alignment_Deskewing.hdmi_align_deskew|bit_slip[*].bitslipper|index[*] 1

This problem has been fixed starting in version 18.0 of the Intel® Quartus® Prime software.