Article ID: 000075414 Content Type: Troubleshooting Last Reviewed: 01/11/2023

Why might I see transmission errors when running a single lane SerialLite III IP core implementation on Intel® Stratix® 10 FPGA hardware?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Serial Lite III Streaming Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might see Transmission Error when running a single lane SerialLite III IP core implementation on Intel® Stratix® 10 FPGA on hardware if Required idle cycles between bursts parameter value is set to 2.

    Resolution

    To work around this problem, change Required idle cycles between bursts value to 1. Regenerate and recompile.

    This problem is scheduled to be fixed in the next full production release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 3 products

    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 GX FPGA

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