Article ID: 000075412 Content Type: Troubleshooting Last Reviewed: 08/18/2017

Why does the Low Latency 40G IP Core fail timing closure when operating in KR4 mode on Arria 10?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • Low Latency 40G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
  • Low Latency 40G 100G Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the Low Latency 40G MAC IP Core operating in KR4 mode on Intel® Arria® 10 Devices, Timing closure setup failure may be seen due to clocks incorrectly promoted to "Regional" instead of "Periphery" network.

    Resolution

    To work around this problem, add the follow assignments to your projects Quartus® Settings File(.qsf). These additional assignments will force the failing *out_pld_pcs_tx_clk_out and *out_pld_pcs_rx_clk_out clocks on to the periphery network. Note that an assignment is required for each lane.

    set_instance_assignment -name GLOBAL_SIGNAL PERIPHERY_CLOCK -to *e40_inst*g_xcvr_native_insts[*]*twentynm_xcvr_native_inst*inst_twentynm_pcs*_pld_pcs_tx_clk_out
    set_instance_assignment -name GLOBAL_SIGNAL PERIPHERY_CLOCK -to *e40_inst*g_xcvr_native_insts[*]*twentynm_xcvr_native_inst*inst_twentynm_pcs*_pld_pcs_rx_clk_out

    This problem is scheduled to be fixed in a future release of the Quartus Prime software.

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