Description
You might see this warning during the fitter and static timing analysis stages in the Intel® Quartus® Prime Software version 17.0 when compiling a design with the JESD204B standalone IP core targeting an Intel® Arria® 10 device, due to the fact that that the reconfig_clk is unconstrained in the IP.
Resolution
To work around this problem, define the reconfig_clk in the IP SDC file at frequency 100 MHz - 125 MHz.
This problem is fixed starting from the Intel Quartus Prime Software version 17.0.1.