Article ID: 000075405 Content Type: Troubleshooting Last Reviewed: 01/31/2023

Why is BAR addresses greater than 32 bits truncated to 32 bits on my Hard IP for the PCI Express Avalon-MM variant?

Environment

    Intel® Quartus® Prime Pro Edition
    Avalon-MM Cyclone® V Hard IP for PCI Express Intel® FPGA IP
    Avalon-MM Arria® V Hard IP for PCI Express Intel® FPGA IP
    Avalon-MM Arria® V GZ Hard IP for PCI Express Intel® FPGA IP
    Avalon-MM Stratix® V Hard IP for PCI Express Intel® FPGA IP
    Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
    PCI Express
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Critical Issue

Description

Due to a problem with the Avalon-MM Hard IP core for PCI Express*, BAR addresses greater than 32 bits will be truncated to 32 bits only.  The upper bits will be set to zero.

This only affects the downstream direction Rxm ports when operating in 64-bit addressing mode. It does not affect the Txs ports or when operating in 32-bit addressing modes.

 

 

Resolution

This problem is fixed starting with the  Intel® Quartus® Prime Pro Edition Software version 18.0.

Related Products

This article applies to 6 products

Intel® Cyclone® 10 FPGAs
Intel® Cyclone® 10 GX FPGA
Cyclone® V FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs

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