Article ID: 000075402 Content Type: Troubleshooting Last Reviewed: 11/27/2017

Why do I see errors, or link training or speed change failures, on my Stratix 10 Hard IP for PCIe?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the Intel® Stratix® 10 Hard IP for PCI* Express core on ES1 and ES2 L-tiles and ES1 H-tiles, you may see the following:

    - During link training or speed change, the PCIe* Hard IP may not link up to L0 or achieve the target link speed. When the link does not come up, the LTSSM is stuck in the Detect or Polling state.

    - During the normal operation in the L0 state, the receiver may report errors.

    The rate of occurrence for these two events varies depending on system/device characteristics and operating conditions.

     

    Resolution

    To work around this problem on the affected tiles, try reconfiguring the FPGA.

    This problem is fixed on the Production version L- and H-tiles.

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