Article ID: 000075398 Content Type: Troubleshooting Last Reviewed: 11/29/2017

Why does the lane_act bus show incorrect link widths for my Stratix 10 H-tile Hard IP for PCI Express?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    Due to a problem with the Hard IP for PCI Express* on the Intel® Stratix® 10 H-Tile Production devices, you will see incorrect encoding of the lane_act bus as shown in the following table:

    Actual Link Widthlane_act valueLink Width according to the user guide encoding
    x15'b1 0000x16
    x25'b0 0001x1
    x45'b0 0010x2
    x85'b0 0100x4
    x165'b0 1000x8
    Resolution

    To work around this problem, which only affects H-tile production devices, interpret lane_act using the first two columns in table above.

    This problem will be fixed by soft logic in a future Intel® Quartus® Prime software release.

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