Article ID: 000075396 Content Type: Troubleshooting Last Reviewed: 01/23/2018

Why does the Intel® Stratix® 10 Hard IP for PCIe* report incorrect link widths?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to an encoding problem with the link acknowledge logic in Intel® Stratix® 10 H-Tile ES2 devices, link widths will be incorrectly acknowledged as shown below:

    Actual Link WidthLink Acknowledge
    x1x16
    x2x1
    x4x2
    x8x4
    x16x8
    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

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