Article ID: 000075394 Content Type: Troubleshooting Last Reviewed: 01/22/2018

Why does the Low Latency Ethernet 10G MAC's dynamic generated multi-rate example design fail compilation for Stratix 10 device?


  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP

    Critical Issue


    Due to a problem with Intel® Quartus® Prime version 17.1, the Low Latency Ethernet 10G MAC's dynamically generated multi-rate example design will fail compilation if the "Analog Voltage" setting is changed to 1_1V in Low Latency Ethernet 10G MAC example design GUI. 

    The following are the affected multi-rate example design variants:

    1. 10G USXGMII Ethernet Example Design (Intel® Stratix® 10)
    2. 10M/100M/1G/2.5G/10G Ethernet Example Design (Stratix 10)
    3. 1G/2.5G Ethernet with 1588 Example Design (Stratix 10)
    4. 1G/2.5G/10G Ethernet with 1588 Example Design (Stratix 10)

    To work around this problem, launch the IP Parameter Editor of the following IPs from the generated multi-rate example design project, and manually change the setting for "VCCR_GXB and VCCT_GXB support voltage for the Transceiver" to 1_1V. 

    1. Stratix 10 L-Tile/H-tile Transceiver fPLL (Open the .ip files which located in <project_directory>\rtl\pll_fpll and change the settings)
    2. Stratix 10 L-Tile/H-tile Transceiver ATX PLL (Open the .ip files which located in <project_directory>\rtl\pll_atxpll and change the settings)
    3. 1G/2.5G/5G/10G Multi-rate Ethernet PHY (Open the .ip file which located in <project_directory>\rtl\phy and change the settings) 

     This problem has been fixed in Quartus Prime version 17.1.1.



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