Article ID: 000075389 Content Type: Troubleshooting Last Reviewed: 10/30/2017

Why does my Cyclone® 10 GX PCIe Hard IP link width downtrain?

Environment

  • Intel® Cyclone® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When the Intel® Cyclone® 10 GX PCIe Hard IP core receives TS2 training sequences during the Polling.Config state, automatic lane polarity inversion is not guaranteed. The link may train to a smaller than expected link width or may not train successfully. This can affect configurations with any PCIe speed and width.

    Automatic lane polarity inversion is supported when the Cyclone 10 GX PCIe Hard IP receives TS1 training sequences during the Polling.Active state.

    Resolution

    For closed systems where you control both ends of the PCIe link, design the board without lane polarity inversion between the Cyclone 10 GX PCIe Hard IP and the link partner. If the board design is already finalized with lane polarity inversion, use the Automatic Lane Polarity Inversion Soft IP in Quartus® Prime version 17.1 or newer version.

    For open systems where you do not control both ends of the PCIe link, use the Automatic Lane Polarity Inversion Soft IP workaround in Quartus® Prime version 17.1 or newer version. This soft IP does not support Gen1x1 Cyclone 10 GX PCIe Hard IP configuration, Configuration via Protocol, or Autonomous Hard IP mode.

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