When you enable the Enable Control and Status Registers transceiver option in the JESD204B IP, the IP core simulation will fail as the transceiver will be stuck at reset. You may observe in simulation that the tx_serial_data/rx_serial_data signals, or the xcvr_rst_tx_ready/xcvr_rst_rx_ready signals are stuck at 0.
This problem affects the JESD204B IP generated for Arria® 10 and Stratix® 10 devices in Quartus® Prime Standard and Pro edition software versions 17.0 or earlier.
To work around this problem, supply a 100MHz - 125MHz clock to the reconfig_clk port, and define a reset sequence to the reconfig_reset port.
Alternatively, turn off the transceiver reconfiguration options. Note that the IP core testbench does not perform any operations on the transceiver reconfiguration interface.
This problem is scheduled to be fixed in a future version of the Quartus Prime software.