Article ID: 000075376 Content Type: Troubleshooting Last Reviewed: 10/18/2017

Why does the Display Port channel take a long time for successful Link Training?

Environment

    Intel® Quartus® Prime Pro Edition
    DisplayPort Intel® FPGA IP
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Description

Due to a problem with the Native PHY IP core, Display Port channels take a long time before successfully link training.

This problem is due to the Intel® Quartus® Prime software applying incorrect RX PCS settings to the Native PHY IP core, causing unsuccessful word alignment.

Resolution

A patch is available to fix this problem for the Intel® Quartus® Prime Pro and Standard version 16.1.2.  Download and install Patch 2.29 from the appropriate link below.  

Patch 2.29 for Linux : quartus-16.1.2-2.29-linux.run

Patch 2.29 for Windows :  quartus-16.1.2-2.29-windows.exe

Installation instructions  : quartus-16.1.2-2.29-readme.txt

This problem is fixed starting in Quartus Prime software version 17.1.1 and later.

Related Products

This article applies to 4 products

Intel® Arria® 10 GX FPGA
Intel® Arria® 10 GT FPGA
Intel® Arria® 10 SX SoC FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs

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