Why does the Low Latency Ethernet 10G MAC's dynamic generated 10GBASE-R Register Mode design example fail timing in Intel® Arria® 10 device?

Due to a problem in he Intel® Quartus® Prime Software version 17.0 and above, the Low Latency Ethernet 10G MAC's dynamically generated 10GBASE-R Register mode design example mihgt fail timing when statistics collection is enabled.

To work around this problem, add the following sdc constraint in the altera_eth_top.sdc file: 

if {$::quartus(nameofexecutable) == "quartus_fit"} {

  set_clock_uncertainty -from dut_inst|wrapper_inst|baser_inst|xcvr_native_a10_0|rx_pma_clk -to dut_inst|wrapper_inst|baser_inst|xcvr_native_a10_0|rx_clkout -hold -add -100ps

} 

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.0.