Why does the Low Latency Ethernet 10G MAC's dynamic generated 10GBASE-R Register Mode example design fail timing in Arria 10 device?

Due to a problem in Intel® Quartus® Prime version 17.0 and above, the Low Latency Ethernet 10G MAC's dynamically generated 10GBASE-R Register mode example design may fail timing when statistics collection is enabled.

To work around this problem, add the following sdc constraint in altera_eth_top.sdc file: 

if {$::quartus(nameofexecutable) == "quartus_fit"} {

  set_clock_uncertainty -from dut_inst|wrapper_inst|baser_inst|xcvr_native_a10_0|rx_pma_clk -to dut_inst|wrapper_inst|baser_inst|xcvr_native_a10_0|rx_clkout -hold -add -100ps

} 

This problem is scheduled to be fixed in a future version of the Intel Quartus Prime software.