Article ID: 000075365 Content Type: Troubleshooting Last Reviewed: 05/12/2017

Why does the Hard IP for PCI Express keep dl_up asserted, and transmit incorrect TS1 ordered sets when in the Disabled state?


  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express

    Critical Issue


    Due to problems with the Hard IP for PCI Express* IP core in Arria® 10, the core does not deassert the dl_up signal while in the Disabled LTSSM state.  Further, the core does not transmit the expected EIOS/Electrical Idle ordered sets when entering the Disabled state.


    You should qualify dl_up with the LTSSM disabled state, and ignore dl_up in the disabled state (that is, consider dl_up to be deasserted while in the Disabled state).

    There is no work around for the incorrect ordered sets. That behavior may cause the link partner to exit the disabled state and return to the Detect state.

    These problems are not scheduled to be fixed in any future Quartus® Prime software release.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs