Article ID: 000075364 Content Type: Troubleshooting Last Reviewed: 07/21/2017

When should I enable the Soft DFE Controller IP for Arria 10 PCIe HIP?

Environment

  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Intel® Arria® 10 PCI Express* Hard IP core configured in Gen3 mode may exhibit several link recoveries or down-train due to bit errors.

    Starting in Quartus® Prime v17.0, there is an option in the Arria 10 PCIe Hard IP component to enable the Soft DFE Controller IP to improve link stability for Gen3 Endpoint mode. For Gen3 Rootport mode, this IP support is expected a later release of the Quartus Prime software. The Soft DFE Controller IP is recommended for Arria 10 open systems, and for closed systems that have short reflective links.

    The Soft DFE Controller IP is not supported for Autonomous HIP or CvP modes.

    Resolution

    To enable the Soft DFE Controller IP for Arria 10 Gen3 mode, follow this procedure (in either Quartus Prime Pro or Quartus Prime Standard):

    • Open the System Contents view in Qsys.
    • Select the Hard IP (DUT).
    • Go to the PHY Characteristics tab.
    • Check the "Enable Soft DFE controller IP" check-box.
    • Regenerate the PCIe Hard IP.
    • Recompile the design.

     

     

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