Article ID: 000075357 Content Type: Troubleshooting Last Reviewed: 04/06/2017

Why does the RapidIO II IP Core transmit when TX digital reset is asserted?

Environment

    Intel® Quartus® Prime Pro Edition
    RapidIO II (IDLE2 up to 6.25 Gbaud) Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

Due to a bug in the RapidIO II IP Core, the transceiver can start transmitting 0xBC characters before TX Digital Reset (tx_digitalreset on Arria® 10, or tx_digitalreset_stat on Stratix® 10) has been de-asserted.

This can cause some link partners to incorrectly detect IDLE1 sequence. The detection of IDLE1 sequence is a defined implementation.

Note that RapidIO II IP Core uses IDLE2 sequence.

 

Resolution

This problem has been fixed starting in software version 17.0 of the RapidIO II IP core.

Related Products

This article applies to 12 products

Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V GZ FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Intel® Stratix® 10 FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Arria® V GT FPGA
Arria® V GX FPGA

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