Article ID: 000075351 Content Type: Product Information & Documentation Last Reviewed: 06/01/2017

How can I edit configuration space registers 0x24 to 0x2C of Stratix V, Arria V, and Cyclone V Root Port PCIe HIP?

Environment

  • Arria® V FPGAs and SoC FPGAs
  • Stratix® V FPGAs
  • Cyclone® V FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Arria® V GZ Hard IP for PCI Express Intel® FPGA IP
  • Arria® V Hard IP for PCI Express Intel® FPGA IP
  • Avalon-MM Arria® V GZ Hard IP for PCI Express Intel® FPGA IP
  • Avalon-MM Stratix® V Hard IP for PCI Express Intel® FPGA IP
  • Avalon-MM Arria® V Hard IP for PCI Express Intel® FPGA IP
  • Avalon-MM Cyclone® V Hard IP for PCI Express Intel® FPGA IP
  • Cyclone® V Hard IP for PCI Express Intel® FPGA IP
  • Stratix® V Hard IP for PCI Express Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime software, the configuration registers 0x24, 0x28, and 0x2C of Root Port mode PCI Express* Hard IP (PCIe* HIP) for Stratix® V, Arria® V, and Cyclone® V devices are not writable. All 0 will be returned from these registers.
      0x24 : Prefetchable Memory Base/Limit
      0x28 : Prefetchable Memory Base Upper 32 Bits
      0x2C : Prefetchable Memory Limit Upper 32 Bits

    Resolution

    Open <Qsys file>/synthesis/<Qsys file>.v file with a text editor.
    Change '.prefetchable_mem_window_addr_width_hwtcl (0)' to '.prefetchable_mem_window_addr_width_hwtcl (1)'.
    Close the editor, and compile the Quartus project.

    #Note this problem is for Root Port configurations only. End Points use these register locations for BAR5, Reserved and Subsystem Device ID/Vendor ID. These are programmed by the host, the user application should not try to program these registers. In End Point configurations it is expected to read all 0s from these registers.

    This issue is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.

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