When the CIC core is created in Platform Designer with a multi channel streaming input, the core is created without a channel input. As described in section 3.6.2 of CIC IP Core User Guide, the start of packet is interpreted as a sample from channel 0. If the generated core is connected to a Qsys interconnect block such as a stream splitter, then the CIC core is considered a single channel core because there is no channel input and a channel adapter is inserted. The channel adapter adds logic to only set output valid when on channel 0 and is disabled for all other channels. As a result, the channels greater than 0 are not passed through the filter.
To work around this problem, export the output avalon streaming interface from the Qsys interconnect component and export the CIC filter avalon streaming input. Connect the two components in RTL.
This problem is scheduled to be fixed in a future release of the Quartus II software.