Article ID: 000075326 Content Type: Troubleshooting Last Reviewed: 06/18/2025

Why does the JIC programming of the Stratix® 10 FPGA devices fail after the QSPI flash has previously been accessed in user mode?

Environment

    Intel® Quartus® Prime Pro Edition
    Mailbox Client Intel® Stratix® 10 FPGA IP
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Description

JIC programming of Stratix® 10 FPGA devices may fail after the QSPI flash has previously been accessed in user mode. This happens because the QSPI port in the Secure Device Manager (SDM) has been enabled but has not been disabled after use.

 

 

Resolution

To avoid this, always disable the QSPI interface on the SDM after use. You can disable it by performing the QSPI_CLOSE operation in the Mailbox Client Stratix® 10 FPGA IP.

This problem is fixed in the Quartus® Prime Pro Edition software version 19.1

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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