Article ID: 000075289 Content Type: Troubleshooting Last Reviewed: 02/25/2013

Cyclone V Device Family Pin Connection Guidelines: Known Issues



Issue 99877: Version 1.5

The connection guideline for HPS_CLK2 pins states "This is an optional HPS clock input pin. When you do not use this pin, Altera recommends tying it to GND or leaving it unconnected. If this pin is unconnected, use the Quartus II software programmable options to internally bias this pin.This pin can be reserved as an input tri-state with the weak pull-up resistor enabled, or as an output driving GND."

The HPS_CLK2 is a dedicated input.  When HPS_CLK2 is not used, it must be connecetd to GND.

Issue 67591: Version 1.3

The connection guideline for VREF pins says if voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins. The VREF pin of Cyclone V device is a dedicated power pin, it is not allowed to be used as user I/O when voltage reference I/O standards are not used in the bank. This is fixed in coming release to reflect the correct VREF pin description.


Resolved Issues:

Issue 44314: Version 1.0

The connection guideline for unused GXB_RX pins says to connect to GND through a 10-kΩ resistor.  The 10-kΩ resistor is un-necessary, unused GXB_RX pins can be tied directly to GND.  This is fixed in version 1.2.

Related Products

This article applies to 4 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V ST SoC FPGA