Article ID: 000075283 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the minimum pulse width requirement for DEV_CLRn pin on a Stratix device?

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Description The minimum pulse width requirement for the DEV_CLRn pin for a Stratix® device is 500us.

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This article applies to 1 products

Stratix® FPGAs

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