Article ID: 000075260 Content Type: Troubleshooting Last Reviewed: 06/30/2013

Why aren't my delay chain values back-annotated correctly?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 12.1 and later, back-annotation of delay chain settings does not work correctly. This problem affects designs targeting Stratix® V, Arria® V, and Cyclone® V devices.

    Resolution

    To work around this problem, back annotate delay chain settings using a Tcl script such as the one below. This Tcl script uses D5 delay chain settings as an example.

    load_package chip_planner
    project_open <project_reversion_name>
    read_netlist
    set nodes [get_nodes -type io]

    foreach_in_collection node {
        set name [get_node_info -info name -node ]
        set d5 [get_node_info -info "D5 Delay Chain" -node ]
       
        if { != 0 } {
            set_instance_assignment -name T9_DELAY -to
        }
    }
    project_close

    Related Products

    This article applies to 15 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA
    Stratix® V GT FPGA
    Cyclone® V GX FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA

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