Article ID: 000075248 Content Type: Troubleshooting Last Reviewed: 09/09/2013

{*Name Protected*} (*/stratixv_atoms.vhd: line 5355, position 21) and verilog parameter being overridden {*Name Protected*}.{*Name Protected*} (*/stratixv_atoms_ncrypt.v: line -1, position -1) are not type compatible.

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description You may see this error when simulating a VHDL design in the Cadence NC-Sim software if the VHDL instantiates lower level Verilog HDL files.
Resolution To avoid this error, use the -namemap_mixgen option with the ncelab command.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.