Article ID: 000075236 Content Type: Troubleshooting Last Reviewed: 05/15/2013

Why does my hard memory controller example design simulation fail?


  • Quartus® II Subscription Edition
  • Simulation
    Description If the hard memory controller (HMC) uses one or more unidirectional MPFE ports, then the example design simulation may fail. The problem is due to the example driver performing write and read transactions to the controller regardless of the port direction. For example, if the port is configured as read-only port, the example driver will still issue write requests along with the read requests to the controller. This corrupts the data in memory and leads to the example driver asserting the fail status flag.

    The workaround is as follows:

    1. For the read-only MPFE ports, tie the avl_write_req input to the hard memory controller to 1\'b0.
    2. For the write-only MPFE ports, tie the avl_read_req input to the hard memory controller to 1\'b0.
    3. For all uni-directional MPFE ports, change the TG_ENABLE_READ_COMPARE from 1 to 0 for the traffic generator instantiation in the *_d0.v and *_d0_mp<port>.v files. This turns off the read back data compare.

    This issue will be fixed in a future release of the Quartus® II software.

    Related Products

    This article applies to 1 products

    Cyclone® V E FPGA



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