Article ID: 000075229 Content Type: Troubleshooting Last Reviewed: 01/01/2015

What reset sequence should I follow to fix link training hardware issues in my PCI Express Soft IP Gen2 x4 or x8 design in Stratix IV GX/GT devices?


  • Reset

    If you are experiencing problems with link training or down training in Stratix® IV devices using the PCI Express Compiler in the Quartus II software version 9.1 and later, targeting the software IP block (SIP) in Gen2 x4 or x8 please ensure that your Reset Controller implements the following sequence. Please refer to the diagram below:

    Figure 1. PCI Express Reset Sequence Requirement

    Figure 1
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    1. Assert pll_powerdown for pll_powerdown duration (1) to (2)
    2. When pll_locked asserts (3), de-assert tx_digitalreset (4)
    3. When busy de-asserts (5), de-assert rx_analogreset (6)
    4. Wait 75us after se-asserting rx_analogreset (6), then de-assert rx_digitalreset (7)
    5. pipephydonestatus de-assertion (8) will indicate that the LTSSM_state is transitioning to (9) state
    6. pipephystatus changing to receiver.detected (10) state will preceed the LTSSM_state transitioning to polling (11) state
    7. When the LTSSM_state changes to polling (11) assert rx_digitalreset (12)
    8. Monitor the rx_signaldetect[n-1:0] signals until any one of them asserts (13) and stays asserted for 3ms (14)
    9. When any rx_signaldetect signal has remained asserted for 3ms (14), de-assert rx_digitalreset (15)

    The reset sequence of the PCI Express (PIPE) Function Mode is now completed.


    Related Products

    This article applies to 3 products

    Stratix® IV GX FPGA
    HardCopy™ IV GX ASIC Devices
    Stratix® IV GT FPGA