Article ID: 000075210 Content Type: Troubleshooting Last Reviewed: 03/16/2023

Why am I not able to assign a 3.3 V input to a bank with VCCIO connected to 2.5 V


  • Quartus® II Subscription Edition

    The 3.3-V LVTTL and 3.3-V LVCMOS standards support VCCIO connected to 3.3 V, 3.0 V, or 2.5 V for input operation on Arria® V and Stratix® V device families.

    In versions 11.0 and 11.1 of the Quartus® II software, assigning a pin with a standard that requires VCCIO to be connected to 2.5 V (such as 2.5 V output) and a 3.3-V LVCMOS/LVTTL input will lead to a fitter error.


    Make an I/O standard assignment of 2.5 V to inputs that require the 3.3-V LVCMOS/LVTTL standards.

    The 2.5 V standard input specifications are the same as the 3.3-V specifcations except that Vil is 0.7 V rather than 0.8 V.  See the following device datasheets for more information on input voltage thresholds:

    This problem will be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 5 products

    Stratix® V GS FPGA
    Arria® V GX FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V E FPGA



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