Article ID: 000075203 Content Type: Troubleshooting Last Reviewed: 10/15/2012

Is DCLK a dual-purpose pin in Stratix V, Arria V and Cyclone V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, DCLK is not a dual-purpose pin in the Stratix® V, Arria® V and Cyclone® V device familes, so it is not possible to manually assign a user signal to this pin in the Quartus® II design software.

 
However, if using the ALTASMI_PARALLEL megafunction or the EPCS Controller component in QSys, DCLK will be accessible by these functions in user mode, to faciliate access to an EPCS or EPCQ device.

Related Products

This article applies to 15 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Arria® V GT FPGA
Cyclone® V SE SoC FPGA

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