Article ID: 000075194 Content Type: Product Information & Documentation Last Reviewed: 03/11/2023

How do I select a data width of 16 bits for the DDR3 SDRAM UniPHY IP in the Cyclone® V EPE IP tab?

Environment

    Intel® Quartus® Prime Standard Edition
    DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
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Description

The Cyclone® V EPE IP tab is missing the 16-bit data width option for the DDR3 SDRAM UniPHY IP.

 

 

Resolution

Select 32-bit and manually modify the instantiation in the I/O tab (i.e., adjust pin counts - # dq pin, #dqs pins ) to create a 16-bit instantiation.

Reuse the entries from the 32-bit option for the CLK, PLL, RAM, and Logic tabs to estimate 16-bit power.

Related Products

This article applies to 6 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V ST SoC FPGA
Cyclone® V E FPGA
Cyclone® V SE SoC FPGA

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