Article ID: 000075179 Content Type: Troubleshooting Last Reviewed: 12/11/2012

Why are the M and N counter parameters for my PLL being seen as invalid during synthesis?

Environment

    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Quartus® II Software views parameters and generics as global.  If user created parameters or generics are have the same names as parameters used in Altera IP, then settings can be inadvertently overridden.

Altera PLL Example:

If user created parameters called “M” or ”N” are created at the top level of a design containing Altera PLLs at a lower level in the hierarchy, this can affect the instantiated PLLs and result in errors and unexpected behaviour:

Example Error Message:

Error: <Design Hierarchy Path>:auto_generated|pll1" has port CLK[0] connected but parameters clk0_counter is either unspecified or set to Unused

Resolution

To work around this problem ensure a user defined prefix is added to user parameters to avoid namespace conflicts.

This problem is scheduled to be fixed in a future release of the Quartus II software.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1