Article ID: 000075161 Content Type: Troubleshooting Last Reviewed: 09/02/2014

Why can't I merge multiple SDI IP instances sharing a single Tx PLL when implementing the triple standard protocol on Stratix V, Arria V, and Cyclone V transceiver devices?

Environment

    PLL
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The SDI IP in Triple Standard mode implements PLL reconfiguration to switch datarates on Stratix® V, Arria® V, and Cyclone® V transceiver devices. If more than one IP instance shares a single transceiver Tx PLL, then the XCVR_TX_PLL_RECONFIG_GROUP .qsf assignment is required. Details of this assignment are described in the 'PLL Reconfiguration' section of the Transceiver PHY IP User Guide.

http://www.altera.com/literature/ug/xcvr_user_guide.pdf

Resolution

 

Related Products

This article applies to 10 products

Stratix® V GX FPGA
Cyclone® V SX SoC FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Cyclone® V GT FPGA
Arria® V SX SoC FPGA
Arria® V GZ FPGA
Arria® V GX FPGA
Stratix® V FPGAs

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