Article ID: 000075160 Content Type: Troubleshooting Last Reviewed: 11/21/2011

Deinterlacer and Frame Buffer Connected to DDR3 May Not Work Properly

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

The Deinterlacer and Frame Buffer MegaCore functions may not work properly when connected to a DDR3 SDRAM High Performance Controller MegaCore function.

In some configurations and or with specific input resolutions, the Deinterlacer and Frame Buffer MegaCore functions may issue write and read bursts starting at odd addresses. The DDR3 SDRAM controller uses wrapping bursts for read accesses, consequently the wrong data may be read back from memory.

Systems connecting the Video and Image Processing MegaCore functions to DDR3 SDRAM.

This issue may have unpredictable effects. Typically, the output video is distorted.

Resolution

Turn on Align read/write bursts with burst boundaries in the Frame Buffer and Deinterlacer parameter editors.

This issue will be fixed in a future version of the Video and Image Processing Suite.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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