In simulation, the testbench or bus functional model (BFM) might be unable to send continuous PCI Express® (PCIe) transactions. This inability results in rx_st_valid deasserting between some or all packets on the Avalon®-ST bus.
The Altera® Hard IP for PCI Express® is capable of continuous Avalon-ST packets, but to observe this the testbench or BFM must be capable of sending continuous PCIe transactions. Refer to the attached screenshot for an example of a BFM which sends continuous PCIe transactions.
You must modify your testbench or BFM to supply continuous PCIe transactions to keep rx_st_valid asserted between Avalon-ST packets.
For example throughput measurements, please refer to the following application note pages: