Article ID: 000075157 Content Type: Error Messages Last Reviewed: 09/11/2012

Error: Pin is incompatible with I/O bank . Pin uses I/O standard <I/O standard>, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO <voltage>.


  • I O

    The Quartus® II software version 7.1 SP1 or 7.2 may incorrectly generate this message when you perform I/O assignment analysis or use the Live I/O Check feature, if you have assigned a differential clock input to a column I/O bank of a Stratix® III device.

    In Stratix III devices, any differential clock input in a column I/O bank is independent of the VCCIO voltage; the power supply for the differential clock input buffer is VCC_CLKIN. As an example, you can assign an LVDS clock input to an I/O bank regardless of the VCCIO settings in that bank.

    There are patches available to fix this problem. Use mySupport to request patch number 1.32 for the Quartus II software version 7.1 SP1 on Windows or Linux, or patch number 0.11 for the Quartus II software version 7.2 on Windows. This incorrect message will also be fixed in a future version of the Quartus II software.

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    This article applies to 1 products

    Stratix® III FPGAs