Article ID: 000075150 Content Type: Error Messages Last Reviewed: 04/11/2016

Error (175020): Illegal constraint of fractional PLL to the region (0, 98) to (0, 105): no valid locations in region

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description You may see the above Quartus® II fitter error if a Stratix® V fractional PLL in "Operation mode = direct" is driven by the tx_clkout of a transceiver channel located in the lower triplet of a transceiver bank. This is a known problem with the Quartus II software which incorrectly enables "Operation mode = normal" in the fractional PLL.
    Resolution

    Manually set the fractional PLL Operation mode to direct through a QSF assignment. The following is an example of the QSF assignment:

    set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "pcie_pll:inst1|pcie_pll_0002:pcie_pll_inst|altera_pll:altera_pll_i|general[0].gpll"

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    Intel® Programmable Devices