Article ID: 000075148 Content Type: Troubleshooting Last Reviewed: 10/31/2016

Arria V, Arria V GZ, Cyclone V, and Stratix V PCI Express User Guides Show Incorrect Timing for the Transaction Layer Configuration Space Signals

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Arria V, Arria V GZ, Cyclone V, and Stratix V PCI Express User Guides for the Avalon-ST and Avalon-MM interfaces show an incorrect timing diagram for Transaction Layer Configuration Space Signals (tl_cfg*). The Configuration Space Register Access Timing shows tl_cfg_add and tl_cfg_ctl updating every cycle. However, depending on your parameterization, these signals actually update every four or eight clock cycles. In addition, this interface is a multi-cycle path. Depending on the parameters you select, you must sample this interface in the middle of a four- or eight-cycle window to ensure proper operation.

    Resolution

    This problem is fixed in October 31, 2016 versions of these user guides.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices