This problem affects Arria V And Cyclone V HPS interfaces.
The NC-Sim simulator requires that each file contain a time scale directive. Some of the Altera Verilog or System Verilog files for HPS simulation might be missing the required time scale.
The workaround for this issue is to add the following to any files that are missing the time scale directive:
timescale 1 ps / 1 ps
This issue will be fixed in a future version.