Article ID: 000075100 Content Type: Troubleshooting Last Reviewed: 04/19/2024

Why does compilation report in the Quartus® Prime Pro Edition Software not showing PLL Freq Min Lock and PLL Freq Max Lock?

Environment

    Intel® Quartus® Prime Pro Edition
    IOPLL Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

In the Quartus® Prime Pro Edition Software, the PLL Freq Min Lock, PLL Freq Max Lock reports for IOPLL, and Fractional PLL (fPLL) are removed from the compilation report for the following device family:

  • Agilex™ FPGA
  • Stratix® 10 FPGA
  • Arria® 10 FPGA
  • Cyclone® 10 GX FPGA
Resolution

This problem is fixed in Quartus® Prime Pro Edition Software

Related Products

This article applies to 4 products

Intel® Cyclone® 10 GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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