Why single PLL cannot drive LVDS channels on different edge bank at the same time for Intel® Cyclone® V devices?

While Intel® Cyclone® V handbook says that "Each PLL can drive all the LVDS channels located at the same edge of the chip", if the single PLL is driving LVDS channel at both top/bottom and left/right edge at the same time it will produce fitter error during Intel® Quartus® compilation and it will fail the project. You may see "Error 14566: Could not place periphery component(s) due to conflicts with existing constraints".

To work around, do not drive PLL to LVDS channels on different edge.
User should carefully assign the PLL and check the pin placement to ensure the design meets the design rule. You can refer to "Guideline: Using LVDS Differential Channels" in Intel® Cyclone® V handbook.