When you instantiate more than one SPI 4.2 MegaCore® function in your design and modify the generated SDC file accordingly, you may see the following info in the Quartus II software:
Info (332164): Evaluating HDL-embedded SDC commands
Info (332165): Entity *rx_data_phy_altlvds_lvds_rx1
Info (332166): create_generated_clock -name lvds_gen_pll_scanclk -source [get_pins -compatibility_mode *clk_div_cntr|*[0]|clk] -divide_by 2 [get_registers *clk_div_cntr|*[0]*]
Warning (332048): Ignored create_generated_clock: Argument -source is a collection with more than one object
…
Warning (332060): Node: *data_phy_altlvds_cntr123:clk_div_cntr|counter_reg_bit[0] was determined to be a clock but was found without an associated clock assignment.
The embedded SDC commands are ignored due to the multi-match of the source and target. Hence, the respective clock assignment is not generated.
You should manually add the related SDC commands to the SDC file of the project:
create_generated_clock -name <clock_name> -source [get_pins -compatibility_mode <inst_name>*clk_div_cntr|*[0]|clk] -divide_by 2 [get_registers <inst_name>*clk_div_cntr|*[0]*]
For example, if there are two instance in your design, there would be two SDC commands to add to the SDC file. You should name the two clocks separately and modify the inst_name corresponding to the name of your instance in your design.