Critical Issue
When you regenerate the Altera® I/O Phase-Locked Loop (Altera IOPLL) IP core in the Quartus® Prime software version 15.1, the name of a PLL in the netlist might change. As a result, the Quartus Prime software might ignore any Quartus Prime Settings File (QSF) assignments or Synopsys Design Constraint (SDC) constraints containing the modified PLL name.
For example, the name of the PLL might change from
u0|iopll_0|altera_pll_i|general[0].gpll~IOPLL
to
u0|iopll_0|altera_pll_i|twentynm_pll|iopll_inst
If your design contains any QSF assignments or SDC constraints that target I/O PLL nodes, check the names of the PLLs and make any necessary updates.
In the Altera IOPLL IP parameter editor, ensure that you fill in the Clock
Name field for the output clock. The PLL name change issue does not
affect the SDC clock names produced by derive_pll_clocks
as long as the
Clock Name field is not blank.
Altera recommends checking the clock names to make sure they remain consistent when you migrate your design to the Quartus Prime software version 15.1.