Article ID: 000075075 Content Type: Troubleshooting Last Reviewed: 03/24/2023

Why do I get an error on port mapping of the "use_rx_rate_match" parameter of the XAUI PHY Intel® FPGA IP?


  • Quartus® II Subscription Edition

    There is a known issue with the XAUI PHY Intel® FPGA IP "use_rx_rate_match" parameter in the generated HDL from the parameter editor, in which the parameter is in the wrong position within the parameter listing causing an error within the Quartus® II software.

    This problem was introduced in the Quartus II software v11.0 and persists in v11.0sp1 and v11.1.  Affected devices include all Stratix® IV, Arria® II, Cyclone® IV, and HardCopy® IV device variants that include transceivers.


    A workaround for v11.0 exists in which the "use_rx_rate_match" parameter position can be manually changed in all generated HDL in which it is present to correspond to the same position in all instantiations.  This workaround is also valid for Quartus II software v11.0sp1 and v11.1.  However, a patch exists that can be applied to the Quartus II software v11.0sp1.  This patch can be downloaded using the following links:

    Related Products

    This article applies to 9 products

    HardCopy™ IV GX ASIC Devices
    Cyclone® IV GX FPGA
    Stratix® IV FPGAs
    Arria® II GX FPGA
    Arria® II GZ FPGA
    Arria® II FPGAs
    Cyclone® IV FPGAs
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA