Article ID: 000075068 Content Type: Troubleshooting Last Reviewed: 02/11/2013

Why do I see the Altera_PLL megafunction output clocks operate intermittently in functional simulation?

Environment

    Quartus® II Subscription Edition
    Simulation
    PLL
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Description Due to a problem in the Quartus® II software version 10.0 and later, you may see the output clocks from an Altera_PLL megafunction operate intermittently in functional simulation even though the locked signal is asserted.  You may see periodic failures for the output clocks depending on the calculated value for the VCO frequency. This problem occurs because the simulation model is limited to 1 ps resolution for the Altera_PLL.
Resolution If you are affected by this limitation when simulating the Altera_PLL megafunction, adjust the input clock period by increasing or decreasing the input clock period by 2-ps increments in the simulation test bench until the VCO period can be calculated within a resolution supported by the simulation models.

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