Article ID: 000075043 Content Type: Troubleshooting Last Reviewed: 05/10/2023

Why are my Input Delay Chain assignments not correctly reflected in the Timing Analyzer when using Intel® Arria® 10 and Intel® Cyclone® 10 GX devices?

Environment

    Intel® Quartus® Prime Pro Edition
    Generic Component
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

To ensure the user assigned Input Delay Chain settings for I/O are reflected in the Timing Analyzer, follow these steps in the Resolution section.

Resolution

Enable the Fast Input register for the respective pins in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

Related Products

This article applies to 2 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 GX FPGA

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