Article ID: 000075034 Content Type: Troubleshooting Last Reviewed: 03/20/2023

Why doesn't Auto Open-Drain pins option take effect on Intel Agilex® 7 FPGA Hard Processor System (HPS)?


  • Intel® Quartus® Prime Pro Edition

    When you set the Auto Open-Drain Pins option for Intel Agilex® 7 FPGA Hard Processor System(HPS) I/Os in the Assignment Editor, the assignment will not take effect on the assigned I/Os. This is due to Intel Agilex 7 FPGA HPS currently does not support the control of open-drain setting for the I/O through Assignment Editor.



    To enable the open-drain setting for Intel Agilex 7 FPGA HPS, you need to change the parameters during instantiation of the HPS RTL and the open-drain setting has to be established in the HPS IP. The workaround steps for enabling the open drain setting on HPS I/Os are as follows:

    1. Generate the HPS IP.
    2. Locate the *_interface_generator*.sv that was created. Typical location is in directory /*/ip/<qsys_top>/<hps_ip_name>/intel_agilex_interface_generator_<ver>/agilex_hps_intel_agilex_interface_generator_<ver>_<random>.sv.
    3. Locate the tennm_io_obuf instance related to the I/O which you want to modify (All I/Os have an obuf and ibuf - only the obuf need to be modified).
    4. Add the parameter settings .open_drain_output("true") to the instance.
    5. Perform a full recompilation on your design.

    The following shows an example of what you would see in the .sv file (the bolded portion is what you would have to add):

    wire [0:0] gpio1_io4_out;

    tennm_io_obuf #(.open_drain_output("true")) hps_gpio1_io4_obuf(





    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs