Article ID: 000075024 Content Type: Troubleshooting Last Reviewed: 05/16/2013

CPRI IP Core Variations That Target a Stratix V Device Do Not Achieve Timing Closure

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

CPRI IP core variations that target a Stratix V device fail to achieve timing closure with the default Quartus II Fitter settings. Specifically, they experience hold time violations on the RAM input path.

Resolution

To achieve better timing closure results, perform one of the following actions:

  • Add set_min_delay assignments to overconstrain timing.
  • Try different Quartus II Fitter seeds.

This issue will be fixed in a future version of the CPRI MegaCore function.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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